New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned logic solutions with the flexibility of standard high-level programming methodology. Automated extension of processors and the associated software tools (compilers, debuggers, simulators and real-time operating systems) enables the use of such configurable and extensible processors. At the same time, designing at the level of software and instruction set architecture significantly shortens the design cycle and reduces verification effort and risk.
U.S. Pat. No. 6,282,633, issued Aug. 28, 2001 and entitled, “High Data Density RISC Processor,” U.S. Pat. No. 6,477,683, issued Nov. 5, 2002 and entitled “Automated Processor Generation System for Designing a Configurable Processor and Software,” U.S. Pat. No. 6,477,697, issued Nov. 5, 2002 and entitled “System for Adding Complex Instruction Extensions to a Microprocessor,” and U.S. Pat. No. 7,036,106, issued Apr. 25, 2006 and entitled “Improved Automated Processor Generation System for Designing a Configurable Processor and Software,” all commonly owned by the present assignee and incorporated herein by reference, dramatically advanced the state of the art of microprocessor architecture and design.
More particularly, these previous patents and applications described in detail a high-performance RISC processor, as well as a system that is able to generate a customized version of such a high-performance RISC processor based on user specifications (e.g., number of interrupts, width of processor interface, size of instruction/data cache, inclusion of MAC or multiplier) and implementation goals (e.g., target ASIC technology, speed, gate count, power dissipation, prioritization). The system generates a Register Transfer Level (RTL) representation of the processor, along with the software tools for the processor (compiler, linker, assembler, debugger, simulator, profiler, etc.), and the set of synthesis and place and route scripts to transform the RTL representation into a manufacturable geometric representation. The system further includes evaluation tools that allow for processor extensions to provide hardware support for commonly used functions in the application to achieve an ideal trade-off between software flexibility and hardware performance.
Generally, as shown in FIG. 1, the processor 102 generated by the system can include a configurable core 104 that is substantially the processor described in U.S. Pat. No. 6,282,633, and an optional set of application-specific processor extensions 106, which extensions may be described by Tensilica Instruction Extension (TIE) language instructions, and/or other high level hardware description language instructions, as detailed in the above-referenced applications. The processor and generation system of the above-referenced patents and applications are embodied in products that are commercially available from Tensilica, Inc. of Santa Clara, Calif.
Although the above processor and generation system provided many advantages, the processor was limited by restricting an instruction to perform a single computational task, however complex it may be. Increasing the number of computational tasks which can be performed simultaneously is a key to further improve the performance of embedded systems. To achieve this goal, several prior art microprocessors (e.g., the Intel IA-64 architecture), typically called VLIW machines, were invented to allow multiple operations to be packed into a single instruction for concurrent execution. In such a microprocessor, an instruction contains multiple operational slots, each capable of performing a set of operations independent of the others. The concurrency is achieved by a C/C++ compiler detecting parallel computational operations and packing the operations into VLIW instructions for simultaneous execution, or by the programmer manually grouping operations into VLIW instructions. However, all these prior art VLIW machines are limited to have a fixed instruction set, and cannot be configured to support application-specific extensions.